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This research project aims to address the power challenges of current and emerging high performance computing systems by exploring a comprehensive cross-layer and application-aware strategy that addresses energy/power-efficiency in combination with quality of solutions, performance and reliability and other objectives and tradeoffs. It considers ongoing many-core technologies such as the Intel Many Integrated Core (MIC) architecture and includes exploring application-aware, cross-layer power/performance optimizations, modeling power and performance of large systems, and programming language abstractions and runtime systems for large-scale systems.
1) Stephen Poole, Oak Ridge National Laboratory
2) Rajeev Muralidhar, Intel Labs, India
3) Hari Seshadri, Intel Labs, India
4) Sunil Sherlekar, Intel Labs, India
1) National Science Foundation
2) Intel Corporation
1) I. Rodero, S. Chandra, M. Parashar, R. Muralidhar, H. Seshadri, S. Poole, "Investigating the Potential of Application-Centric Aggressive Power Management for HPC Workloads", 17th IEEE International Conference on High Performance Computing (HiPC), 2010.
2) K. Elangovan, I. Rodero, M. Parashar, F. Guim, I. Hernandez, "Adaptive Memory Power Management Techniques for HPC Workloads", 18th IEEE International Conference on High Performance Computing (HiPC), 2011.
3) M. Gamell, I. Rodero, M. Parashar, R. Muralidhar, "Exploring Cross-layer Power Management for PGAS Applications on the SCC Platform", 21st International ACM Symposium on High-Performance Parallel and Distributed Computing (HPDC), 2012.